Digital Logic Design
Registers Fundamentals | Shift Registers
Design of a Sequential Circuit - Part 2 (Continued)
Design of a Sequential Circuit
Analysis of Sequential Circuit
Edge Triggered D Flip Flop
Excitation Tables
Edge Triggered JK Flip Flop | T Flip Flop
Clocked SR Flip Flop | Timing Diagram
Gated D Latch | Timing diagram
Gated SR Latch | Timing diagram
SR Latch Timing Diagrams | Waveforms
Comparison between S.R Latch using NOR Gates and NAND Gates
Basic SR Flip Flop using NAND Gates | SR Latch
Basic SR Flip Flop using NOR Gates | SR Latch
Introduction to Sequential Circuits | Flip Flops
4 x 2 Priority Encoder
4x2 Encoder
1x4 Demultiplexer | With Enable Input | 1x8 Demux | Implementation of any function using Demux
1x4 Demultiplexer | Decoder as Demultiplexer
Implementation of a Function using Multiplexers (Continued) | Quadruple 4x1 Multiplexer
Implementation of a Function using Multiplexers
4x1 Multiplexer with Enable Input | 8x1 Multiplexer
Design of 4x1 Multiplexer
3x8 Decoder | Decoder Expansion | Implementation of a function using Decoder
Introduction to Decoders | Design of 2x4 Decoder